The present invention relates to fabrication of semiconductor devices and integrated circuits, and more particularly to fabrication of bipolar and BiCMOS integrated circuits.
In integrated circuits, transistors are typically isolated from each other, and selected transistor regions are interconnected by conductive lines to form a desired circuit. It is desirable to develop isolation techniques that would provide low leakage currents, high punchthrough voltages, low capacitances, a high yield, a small transistor size, a high transistor speed and a low power consumption in bipolar and BiCMOS integrated circuits.
BiCMOS circuits present a particular challenge for fabrication because BiCMOS processes are typically more complex than either bipolar or CMOS processes. In order to simplify BiCMOS processes, the same steps are sometimes used to fabricate both bipolar and MOS transistor features in the process. For example, the same ion implantation step may be used to dope selected regions of both bipolar and MOS transistors. This, however, creates an interdependency between the bipolar and MOS transistors and makes it more difficult to optimize both the bipolar and MOS transistors. Thus, it is desirable to develop a simple and economical BiCMOS process that allows greater decoupling of the bipolar and MOS transistor characteristics.